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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADP3020 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ?analog devices, inc., 2000 high-ef?iency notebook computer power supply controller functional block diagram power-on reset linear controller v in 5.5v to 25v 3.3v q5 2.5v ss3 q1 q2 q3 ss5 q4 5v l1 l2 pwrgd ADP3020 ref 5v linear 3.3v smps 5v smps 1.20v pfo 3.3v smps features wide input voltage range: 4.5 v to 25 v high conversion ef?iency > 96% integrated current sense?o external resistor re quired low shutdown current: 7 a (typical) dual synchronous buck controllers with selectable pwm/power-saving mode operation built-in gate drive boost circuit for driving external n-channel mosfets two independently programmable output voltages fixed 3.3 v or adjustable (1.25 v to vin?.5 v) fixed 5 v or adjustable (1.25 v to vin?.5 v) programmable pwm frequency integrated linear regulator controller extensive circuit protection functions 38-lead tssop package applications notebook computers and pdas portable instruments general purpose dc-dc converters general description the ADP3020 is a highly ef?cient dual synchronous buck switch- ing regulator controller optimized for converting the battery or adapter input into the system supply voltages required in note- book computers. the ADP3020 uses a dual-mode pwm/power saving mode architecture to maintain ef?ciency over a wide load range. the oscillator frequency can be programmed for 200 khz, 300 khz, or 400 khz operation, or it can be synchro- nized to an external clock signal of up to 600 khz. the ADP3020 provides accurate and reliable short circuit pro- tection using an internal current sense circuit, which reduces cost and increases overall ef?ciency. other protection features include programmable soft-start, uvlo, and integrated output undervoltage/overvoltage protection. the ADP3020 contains a linear regulator controller that is designed to drive an external p-channel mosfet or pnp transistor. the linear regulator output is adjustable, and can be used to generate the auxiliary voltages required in many laptop designs.
? rev. 0 ADP3020?pecifications (@ t a = ?0 c to +85 c, vin = 12 v, ss5 = ss3 = intvcc, intvcc load = 0 ma, ref load = 0 ma, mode = 0 v, sync = 0 v, sd = 5 v, unless otherwise noted.) parameter symbol conditions min typ max unit internal 5 v regulator intvcc input voltage range 5.5 25 v 5 v voltage t a = 25 c 4.95 5.025 5.15 v line regulation 5.5 v vin 25 v 0.3 mv/v total variation line, temp 4.8 5.2 v switchover voltage auxvcc from low to high 4.65 4.75 4.85 v switchover hysteresis auxvcc from high to low 100 mv undervoltage lockout intvcc falling 3.6 3.8 4.2 v threshold voltage undervoltage lockout 120 mv hysteresis reference output voltage 2 ref 5.5 v vin 25 v 1.185 1.197 1.209 v supply current i q shutdown current sd = 0 v 7 15 a standby current ss3 = ss5 = sd2 = 0 v 250 400 a sd = 5 v quiescent current no loads, mode = 5 v 0.95 1.8 ma (pwm mode) ss3 = ss5 = sd2 =5 v fb5 = fb3 = fb2 = 1.25 v, adj/ fx5 = adj/ fx3 = 5 v quiescent current no loads, mode = 0 v 650 a (power-saving mode) ss3 = ss5 = sd2 = 5 v fb5 = fb3 = fb2 = 1.25 v, adj/ fx5 = adj/ fx3 = 5 v oscillator frequency f osc sync = agnd 176 200 224 khz sync = ref 264 300 336 khz sync = intvcc 352 400 448 khz sync input frequency range 230 600 khz input low voltage 3 t f 200 ns 0.4 v input high voltage 3 t r 200 ns 4.6 v input current sync = ref 1.2 a power good pwrgd output voltage in regulation 10 k ? pull-up to 5 v 4.8 v output voltage out of regulation 10 k ? pull-up to 5 v 0.4 v fb5 < 90% of nominal output value pwrgd trip threshold fb5 rising C8 C4 C2 % pwrgd hysteresis fb5 falling 4 % cpor pull-up current cpor = 1.2 v 2.5 a error amplifier dc gain 67 db gain-bandwidth product gbw 10 mhz input leakage current i ean adj/ fx5 = adj/ fx3 = 5 v 200 na main smps controllers fixed 5 v output voltage fb5 pwm mode 5.5 v vin 25 v, adj/ fx5 = 0 v 4.90 5.0 5.10 v power-saving mode 5.5 v vin 25 v, adj/ fx5 = 0 v 4.925 5.025 5.125 v fixed 3.3 v output voltage fb3 pwm mode 5.5 v vin 25 v, adj/ fx3 = 0 v 3.234 3.3 3.366 v power-saving mode 5.5 v vin 25 v, adj/ fx3 = 0 v 3.250 3.316 3.382 v
? rev. 0 ADP3020 parameter symbol conditions min typ max unit adjustable output voltage pwm mode ean5, 5.5 v vin 25 v, 1.173 1.197 1.221 v ean3 adj/ fx5 = adj/ fx3 = 5 v power-saving mode fb5, fb3 5.5 v vin 25 v, 1.179 1.203 1.227 v adj/ fx5 = adj/ fx3 = 5 v output voltage adjustment range 3 fb5, fb3 adj/ fx5 = adj/ fx3 = 5 v 1.25 vinC0.5 v current limit threshold (pwm mode) clset5 = clset3 = floating 5.5 v vin 25 v, t a = 25 c547290mv clset5 = clset3 = 0 v 5.5 v vin 25 v, t a = 25 c 115 144 173 mv current limit threshold (power-saving mode) clset5 = clset3 = floating 5.5 v vin 25 v, t a = 25 c16mv clset5 = clset3 = 0 v 5.5 v vin 25 v, t a = 25 c35mv power-saving mode trip threshold clset5 = clset3 = 0 v, t a = 25 c28 mv soft-start current ss3 = ss5 = 3 v 4 a soft-start turn-on threshold ss5, ss3 0.7 1.2 1.8 v feedback input leakage current i fb adj/ fx5 = adj/ fx3 = 5 v, 200 na fb = 1.2 v maximum duty cycle 3 d max vin = 5.5 v, sync = agnd 94 99 % transition time (drvh/drvl) rise t r c load = 3000 pf, 10%C90% 40 70 ns fall t f c load = 3000 pf, 90%C10% 40 70 ns logic input low voltage mode, sd , adj/ fx3 , adj/ fx5 0.6 v logic input high voltage mode, sd , adj/ fx3 , adj/ fx5 2.4 v linear regulator controller feedback threshold fb2 1.176 1.20 1.224 v sd2 pull-up current sd2 sd2 = 1.2 v 4 a sd2 threshold 0.7 1.2 1.8 v current sinking capability drv2 drv2 = 2 v, fb2 = 1 v, sd2 = 5 v 20 45 ma fb2 input leakage current i fb fb2 = 1.2 v 50 na power-fail comparator pfi input threshold pfo from high to low 1.176 1.20 1.224 v pfi input hysteresis 24 mv pfi input current 200 na pfo high voltage 10 k ? pull-up to 5 v 4.8 v pfo low voltage 10 k ? pull-up to 5 v 0.4 v fault protection output overvoltage trip threshold with respect to nominal output 115 120 125 % output undervoltage lockout threshold with respect to nominal output 75 80 85 % notes 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. 2 the references line-regulation error is insigni?cant. the reference cannot be used for external load. 3 guaranteed by design, not tested in production. speci?cations subject to change without notice.
ADP3020 ? rev. 0 pin function descriptions pin no. mnemonic function 1 cs5 current sense input for top n-channel mosfet of the 5 v buck converter. connect to the drain of the top n-channel mosfet. 2 fb5 feedback input for the 5 v buck converter. connect to the output sense point in ?xed output mode. connect to an external resistor divider in adjustable output mode. 3 ean5 inverting input of the error ampli?er of the 5 v buck converter. use for external loop compensation only in ?xed output mode. in adjustable output mode, connect to an external resistor divider. 4 eao5 error ampli?er output for the 5 v buck converter. 5 adj/ fx5 ttl logic input. when adj/ fx5 = 0 v, ?xed output mode, connect fb5 to the output sense point. when adj/ fx5 = 5 v, adjustable output mode, connect fb5 to the external resistor divider. 6 ss5 soft start for the 5 v buck converter. also used as an on/off pin. 7 clset5 current limit setting. a resistor can be connected from agnd to clset5. a minimum current limit is obtained by leaving it unconnected. a max current limit is obtained by connecting it to agnd. 8 ref 1.2 v bandgap reference. bypass it with a capacitor (1 nf typical) to agnd. ref cannot be used directly with an external load. 9 agnd analog signal ground. 10 clset3 current limit setting. a resistor can be connected from agnd to clset3. a minimum current limit is obtained by leaving it unconnected. a max current limit is obtained by connecting it to agnd. 11 mode ttl logic input. mode = 5 v, always in constant frequency pwm mode; mode = 0 v, pwm mode at moderate and heavy loads, and power saving (psv) mode at light load. 12 sync oscillator synchronization and frequency select. f osc = 200 khz, when sync = 0 v; f osc = 300 khz, if sync is tied to the ref pin; f osc = 400 khz, when sync = 5 v. oscillator can be synchronized with an external source through the sync pin. 13 ss3 soft start for the 3.3 v buck converter. also used as an on/off pin 14 adj/ fx3 ttl logic input. when adj/ fx3 = 0 v, ?xed output mode, connect fb3 to the output sense point. when adj/ fx3 = 5 v, adjustable output mode, connect fb3 to external resistor divider. 15 eao3 error ampli?er output for the 3.3 v buck converter. 16 ean3 error ampli?er inverting input of the 3.3 v buck converter. use for external loop compensation only in ?xed output mode. in adjustable output mode, connect to an external resistor divider. 17 fb3 feedback input for the 3.3 v buck converter. connect to output sense point in ?xed output mode. connect to an external resistor divider in adjustable output mode. 18 cs3 current sense input for top n-channel mosfet of the 3.3 v buck converter. it should be con- nected to the drain of the n-channel mo sfet. 19 pfi the (C) input of a comparator that can be used as a power fail detector. the positive input is connected to the 1.20 v reference. there is a 24 mv hysteresis for this comparator. 20 pfo open drain output. this pin will sink current when the pfi pin is lower than 1.20 v. otherwise, pfo is floating. 21 pwrgd power good output. pwrgd goes low with no d elay, whenever the 5 v output drops 8% below its nominal value. when the 5 v output is within C4% of its nominal value, pwrgd will be released after a time delay determined by the timing capacitor on the cpor pin. 22 cpor connect a capacitor between cpor and agnd to set the delay time for the pwrgd pin. a 2.5 a pull-up current is used to charge the capacitor. a manual reset ( mr ) function can also be implemented by grounding this pin. 23 sd2 shutdown input for the linear regulator controller. 24 fb2 feedback for the linear regulator controller. 25 drv2 open collector output for the linear regulator controller. 26 bst3 boost capacitor connection for high side gate driver of the 3.3 v buck converter. 27 drvh3 high side gate driver for 3.3 v buck converter. 28 sw3 switching node (inductor) connection of the 3.3 v buck converter. 29 drvl3 low side gate driver of 3.3 v buck converter. 30 vin main supply input (4.5 v to 25 v).
ADP3020 ? rev. 0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADP3020 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin function descriptions (continued) pin no. mnemonic function 31 intvcc linear regulator bypass for the internal 5 v ldo. bypass this pin with a 4.7 f capacitor to agnd. 32 auxvcc supply switch over. when auxvcc > 4.75 v, and both of the switchers are in power saving mode, the internal 5 v ldo is turned off. the chip is powered by auxvcc pin. there is a 2% hysteresis for this pin. 33 sd shutdown control input, active low. if sd = 0 v, the chip is in shutdown with very low quiescent cur- rent. for automatic start-up, connect sd to v in directly. 34 pgnd power ground. 35 drvl5 low side driver for 5 v buck converter. 36 sw5 switching node (inductor) connection for 5 v buck converter. 37 drvh5 high side gate driver for 5 v buck converter. 38 bst5 boost capacitor connection for high side gate driver of the 5 v buck converter. absolute maximum ratings * vin to agnd . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +27 v agnd to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 v intvcc . . . . . . . . . . . . . . . . . . . . . . agnd C 0.3 v to +6 v bst5, bst3 to pgnd . . . . . . . . . . . . . . . . . C0.3 v to +32 v bst5 to sw5 . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v bst3 to sw3 . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v cs5, cs3 . . . . . . . . . . . . . . . . . . . . . . agnd C 0.3 v to vin sw3, sw5 to pgnd . . . . . . . . . . . . . . C0.3 v to vin + 0.3 v sd . . . . . . . . . . . . . . . . . . . . . . . . . agnd C 0.3 v to +27 v drvl5/3 to pgnd . . . . . . . . . C0.3 v to (intvcc + 0.3 v) drvh5/3 to sw5/3 . . . . . . . . . C0.3 v to (intvcc + 0.3 v) all other inputs and outputs . . . . . . . . . . . . . . . . . . agnd C 0.3 v to intvcc + 0.3 v ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 c/w operating ambient temperature range . . . . C40 c to +85 c junction temperature range . . . . . . . . . . . . C40 c to +150 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c * this is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. pin configuration ordering guide model temperature range package description package option ADP3020aru C40 c to +85 c thin shrink small outline ru-38 14 13 12 11 10 9 8 1 2 3 4 7 6 5 19 18 17 16 15 20 29 28 27 32 31 30 38 37 36 35 34 33 23 22 21 26 25 24 top view (not to scale) ADP3020 bst5 drvh5 sw5 drvl5 pgnd sd auxvcc intvcc vin drvl3 sw3 drvh3 bst3 drv2 fb2 sd2 cpor pwrgd cs5 fb5 ean5 eao5 pfi ss5 clset5 ref agnd clset3 mode sync ss3 pfo eao3 ean3 fb3 cs3 adj/ fx3 adj/ fx5
ADP3020 ? rev. 0 control logic intvcc drv2 fb2 sd2 cpor pwrgd agnd sync + cs5 2.5v 3.3v 1.2v intvcc ?mv 1.22v q r s duplicate for second controller shutdown 1.2v 2.5v on5 power on reset ss5 eao5 ean5 1.2v 1.2v 1.44v 0.96v oc fb5 fb5 drvl5 sw5 v out5 5v 1.2v ref input 5v +5v linear reg auxvcc clset5 bst5 4.7v drvh5 vin 1.2v 200khz/ 300khz/ 400khz osc adj/ fx5 + 4 a pgnd 0.7 a mode 14mv 72mv ADP3020 sd 1.18v 30 33 32 31 8 9 11 12 21 22 25 24 23 6 5 4 3 37 35 36 38 7 2 1 pfo pfi + 19 1.20v 20 4 a 1.2v ref ulvo + + + +2% + + + 2% 0% ea + + + 34 + + +20% + 20% + + figure 1. block diagram (all switches and components are shown for fixed output operation)
ADP3020 7 rev. 0 typical performance characteristics output current a 100 efficiency % 90 80 70 60 50 0.01 0.1 1 10 v in = 6v v in = 15v figure 2. ef ciency vs. 5 v output current output current a 100 efficiency % 90 80 70 60 50 0.01 0.1 1 10 v in = 6v v in = 15v figure 3. ef ciency vs. 3.3 v output current output current a 100 efficiency % 90 80 70 60 50 0.01 0.1 1 10 v in = 6v v in = 15v figure 4. ef ciency vs. 2.5 v output current output current a 100 efficiency % 90 80 70 60 50 0.01 0.1 1 10 v in = 6v v in = 15v figure 5. ef ciency, 1.5 v output current input voltage v 5 current a 10 15 20 800 1000 1200 600 25 +85 c +25 c 40 c figure 6. pwm mode input current vs. input voltage input voltage v 5 current a 10 15 20 900 400 25 800 700 600 500 +85 c +25 c 40 c figure 7. psv mode input current vs. input voltage
ADP3020 8 rev. 0 input voltage v 5 current a 10 15 20 200 250 300 100 25 150 +25 c 40 c +85 c figure 8. input standby current vs. input voltage input voltage v 5 current a 10 15 20 2 3 10 0 25 +25 c 40 c 1 +85 c 6 7 4 5 8 9 figure 9. input shutdown current vs. input voltage ambient temperature c 40 frequency khz 10 20 50 295 315 290 305 300 310 80 sync = ref v in = 25 v in = 12 v in = 7.5 v in = 5.5 figure 10. pwm mode oscillator frequency vs. temperature ambient temperature c 40 current limit threshold mv 30 20 10 50 250 0 150 100 200 v in = 5.5v to 25v clset = gnd 0 1020304050607080 figure 11. current limit threshold vs. temperature ambient temperature c 40 reference output v 30 20 10 1.180 1.210 1.190 1.185 1.195 0 1020304050607080 1.200 1.205 v in = 5.5v to 25v figure 12. reference output vs. temperature ch1 = 3.3v output ch2 = 2.5v output ch3 = ss3 ch4 = ss5 t [] ch1 2.00v ch2 1.00v m 200 ms ch4 740mv ch3 1.00v ch4 1.00v v in = 12v tek stop: single seq 250 s/s figure 13. soft-start sequencing
ADP3020 9 rev. 0 ch1 = 5v output ch2 = i out = 10ma to 3a t [] ch1 200mv ch2 2.00v m 200 s ch2 1.88v stop figure 14. power-saving mode, transient response t [] ch1 200mv ch2 5.00v m 400 s ch2 1.90v ch1 = 5v output (i out = 20ma) ch2 = sw5 stop figure 15. power-saving mode, waveforms ch1 = 5v output ch2 = i out = 10ma to 3a t [] ch1 200mv ch2 2.00v m 200 s ch2 1.88v stop figure 16. pwm mode, transient response ch1 ch2 t [] ch1 10.0v ch2 200mv m 5.00ms ch1 10.8v tek stop: single seq 250 s/s figure 17. v in = 7.5 v to 22 v transient, 2.5 v output, ch1 input voltage, ch2 output voltage
ADP3020 10 rev. 0 theory of operation the ADP3020 is a dual-mode, step-down power supply controller for notebook computers or similar battery-powered applications. the device contains two synchronous step-down buck control- lers and a linear regulator controller. the buck controllers in the ADP3020 have the ability to provide either ?xed 3.3 v and 5 v outputs or independently adjustable (1.25 v to vinC0.5 v) out- puts. high ef?ciency over a broad load range is achieved by using a proprietary dual-mode pwm/power-saving (psv) mode architec- ture. ef?ciency is further improved by deleting the external current sense resistor, which is the main contributor to loss during high current, low output voltage conditions. circuit description dual-mode architecture the ADP3020 contains two independent dual-mode, synchro- nous buck controllers. traditional constant frequency pwm buck converters suffer from relatively low ef?ciency under light load conditions. in order to maintain high ef?ciency over a wide load range, the ADP3020 uses a proprietary dual-mode archi- tecture. at moderate to heavy loads, the buck converter operates in the traditional pulsewidth modulation (pwm) mode. at light loads, psv mode is used to increase system ef?ciency. a propri- etary detection scheme is used for transition from one mode to the other. input current to the high-side mosfet is detected when going from pwm mode to psv mode, and output voltage infor- mation is used when changing from psv mode to pwm mode. when the high-side n-channel mosfet is turned on, the current going through the n-channel mosfet is measured as a voltage between cs and sw. if the peak current through the mosfet is less than 20% of the current limit value set by clset, an internal counter that is based on the oscillator frequency will be started. if the current stays below this threshold for 16 pwm cycles, the buck converter will enter power-saving mode. the counter will automatically reset if the peak current is higher than 20% of the current limit va lue any time prior to when the counter reaches 16. in psv mode, the buck converter works like a window regula- tor. if the output voltage drops below the pwm mode nominal output voltage, the high-side mosfet will be turned on. it will remain on until the output capacitors are charged up to 2% above the pwm mode nominal output voltage. the high-side mosfet will then be latched off until the output capacitors are discharged to the lower threshold. the discharge rate is depen- dent on the output capacitor value and load current. it is important to note that the current limit threshold when in psv mode is approximately 1/4 of the current limit threshold when in pwm mode. if a large load is applied to the converter when in psv mode (for example, larger than the current limit in psv mode), the output will continue to drop due to the lower current limit threshold of psv mode. when the output voltage drops to 2% below the pwm mode nominal voltage, the converter will automatically return to pwm mode. once in pwm mode, the current limit is quadrupled, and the output will be charged up to the nominal level, as long as the load does not exceed the higher pwm current limit. pwm/psv operation (mode) table i shows the summary of the operating modes of the synchro- nous buck controllers. the mode pin determines whether or not the controllers remain in pwm mode under all load conditions. mode can be driven by an external ttl logic signal. when mode is pulled high, psv mode operation is disabled, and the system is always in constant frequency pwm mode. in order to enable psv mode at light loads, the mode pin needs to be pulled low. table i. pwm mode and psv mode load operating mode current mode description high x pwm constant-frequency pwm low heavy pwm constant-frequency pwm low moderate pwm constant-frequency pwm low light psv variable-frequency, burst mode x = dont care. forcing the ADP3020 to always remain in constant frequency pwm mode can be used to reduce interference, as this allows ?ltering of the ?xed fundamental frequency and its harmonics. the operating frequency should be carefully chosen so that both the fundamental and harmonic frequencies are not within sensitive audio or if bands. this is particularly important in noise-sensitive applications such as multimedia systems, cellular phones, com- puters with built-in rf communications, and pdas. if two or more switching regulators are used in a system, it is best to syn- chronize all the switching regulators to a single master regulator or an external clock signal. internal 5 v supply (intvcc) an internal low dropout regulator (ldo) generates a 5 v supply (intvcc) that powers all of the functional blocks within the ic. the total current rating of this ldo is 50 ma. howe ver, this current is used for supplying gate-drive power, and it is not recommended that current be drawn from this pin for other purposes. bypass intvcc to agnd with a 4.7 f capacitor. a uvlo circuit is also included in the regulator. when intvcc < 3.8 v, the two switching regulators and the linear regulator controller are shut down. the uvlo hysteresis voltage is about 120 mv. the internal ldo has a built-in fold-back current limit, so that it will be protected if a short circuit is applied to the 5 v output. if auxvcc is higher than 4.75 v, and both the 5 v and 3.3 v switching regulators are in psv mode, an internal switch will connect intvcc to auxvcc, while simultaneously turning off the internal ldo. auxvcc can be tied to either the 5 v switching regulator output or a separate 5 v voltage source. by doing this, the power loss across the internal ldo is eliminated, and the total ef?ciency in psv mode is improved. when auxvcc = gnd, this automatic power switchover fea- ture will be disabled. internal reference (ref) the ADP3020 contains a precision 1.2 v bandgap reference. bypass ref to agnd with a 1 nf ceramic capacitor. the ref- erence is intended for internal use only. an external voltage buffer is needed if the reference is used for another purpose. boost high side gate drive supply (bst) the gate drive voltage for the high-side n-channel mosfets is generated by a flying-capacitor boost circuit. the boost capacitor connected between bst and sw is charged from the intvcc supply. use only small-signal diodes for the boost circuit.
ADP3020 11 rev. 0 synchronous recti?er (drvl) synchronous recti?cation is used to reduce conduction losses and to ensure proper start-up of the boost gate driver circuit. antishoot-through protection has been included to prevent cross conduction during switch transitions. the low side driver must be turned off before the high side driver is turned on. for typi- cal n-channel mosfets, the dead time is about 50 ns. on the other edge, a dead time of about 50 ns is achieved by an internal delay circuit. the synchronous recti?er is turned off when the current flowing through the low-side mosfet falls to zero when in discontinuous conduc tion (dcm) pwm mode and psv mode. in continuous conduction (ccm) pwm mode, the current flowing through the low-side mosfet never reaches zero, so the synchronous recti?er is turned off by the next clock cycle. oscillator frequency and synchronization (sync) the sync pin controls the oscillator frequency. when sync = 0 v, f osc = 200 khz ; when sync = ref, f osc = 300 khz; when sync = 5 v, f osc = 400 khz. 400 khz operation will minimize external component size and cost while 200 khz opera- tion provides better ef?ciency and lower dropout. the sync pin can also be used to synchronize the oscillator with an exter- nal 5 v clock signal. a low-to-high transition on sync initiates a new cycle. synchronization range is 230 khz to 600 khz. shutdown ( sd ) holding sd = gnd low will put the ADP3020 into ultralow current shutdown mode. for automatic start-up, sd can be tied directly to vin. soft-start and power-up sequencing (ss) ss3 and ss5 are soft start pins for the two controllers. a 4 a pull-up current is used to charge an external soft start capacitor. power-up sequencing can be easily done by choosing different size external capacitors. when ss3/ss5 < 1.2 v, the two switch- ing regulators are turned off. when 1.2 v < ss5/ss3 < 2.6 v, the regulators start working in soft start mode. when ss3/ss5 > 2.6 v, the regulators are in normal operating mode. the con- trollers are forced to stay in pwm mode during the soft-start period. the minimum soft-start time (~20 s) is set by an inter- nal capacitor. table ii shows the ADP3020 operating modes. current limiting (clset) a cycle-by-cycle current limiting scheme is used by monitoring current through the top n-channel mosfet when it is turned on. by measuring the voltage drop across the high-side mosfet v ds(on) , the external sense resistor can be deleted. the current limit value can be set by clset. when clset = floating, the maximum v ds(on) = 72 mv at room temperature; when clset = 0 v, the maximum v ds(on) = 144 mv at room temperature. an external resistor can be connected between clset and agnd to choose a value between 72 mv and 144 mv. the temperature coef?cient of r ds(on) of the n-channel mosfet is canceled by the internal current limit circuitry, so that an accurate current limit value can be obtained over a wide temperature range. in psv mode, the current limit value is reduced to about 1/4 of the value in pwm mode to reduce the inter ference noise to other components on the pc board. output undervoltage protection each swi tching controller has an und ervoltage protection circuit. when the current flowing through the high-side mosfet reaches the current limit continuously for eight clock cycles, and the output voltage is below 20% of the nominal output voltage, both controllers w ill be latched off and will not restart until sd or ss3/ss5 is toggled, or until vin is cycled below 4 v. this feature is disabled during soft start. output overvoltage protection both converter outputs are continuously monitored for overvolt- age. if either output voltage is higher than the nominal output voltage by more than 20%, both converters high-side gate drivers (drvh5/3) will be latched off, and the low-side gate drivers will be latched on, and will not restart until sd or ss5/ss3 are toggled, or until vin is cycled below 4 v. the low-side gate driver (drvl) is kept high when the controller is in off-state and the output voltage is less than 93% of the nominal output voltage. discharging the output capacitors through the main inductor and low-side n-channel mosfet will cause the out- put to ring. this will make the output momentarily go below gnd. to prevent damage to the circuit, use a reverse-biased 1 a schottky diode across the output capacitors to clamp the negative surge. power good output (pwrgd) the ADP3020 also provides a pwrgd signal for the micropro- cessor. during start-up, the pwrgd pin is held low until 5 v output is within C4% of its preset voltage. then, after a time delay determined by an external timing capacitor connected from cpor to gnd, pwrgd will be actively pulled up to intvcc by an external pull-up resistor. cpor can also be used as a manual reset ( mr ) function. when the 5 v output is lower than the preset voltage by more than 8%, pwrgd is immedia tely pulled low. linear regulator controller the ADP3020 includes an onboard linear regulator controller. an external pnp transistor can be used for operation up to 1 a. for higher output current applications, a low threshold pmos can be used as the pass transistor. the output voltage can be set by a resistor divider. the minimum output voltage of the ldo is 1.25 v, while the maximum output voltage depends on where the ldo input is connected and the dropout voltage of the external pass transistor. table ii. operating modes sd ss5 ss3 mode description low x x shutdown all circuits turned off high ss5 < 1.2 v ss3 < 1.2 v standby 5 v and 3.3 v off; intvcc = 5 v, ref = 1.2 v high 1.2 v < ss5 < 2.6 v x run 5 v in soft start high 2.6 v < ss5 x run 5 v in normal operation high x 1.2 v < ss3 < 2.6 v run 3.3 v in soft start high x 2.6 v < ss3 run 3.3 v in normal operation
ADP3020 12 rev. 0 output voltage adjustment fixed output voltages (5 v and 3.3 v) are selected when adj/ fx5 = adj/ fx3 = 0 v. the output voltage of each con- troller can also be set by an external feedback resistor network when adj/fx5 = adj/fx3 = 5 v as shown in figure 18. there should be two external feedback resistor dividers for each con- troller, one for the voltage feedback loop, and one for output voltage monitor. both resistor dividers need to be identical. the minimum output voltage is 1.25 v. the maximum output volt- age is limited only by the minimum supply voltage. remote output voltage sensing can be done for both ?xed and adjustable output voltage modes. the output voltage can be calculated using the following formula: v ref r r out =+ ? ? ? ? ? ? 1 1 2 (1) where ref = 1.2 v , and r 1/ r 2 = r3/r4. ADP3020 drvh drvl fb adj/ fx v in 5v ean r1 r2 r3 r4 v out figure 18. adjustable output mode if the loop is carefully compensated, r3 and r4 can be, removed, and fb and ean can be tied together. application information a typical notebook pc application circuit using the ADP3020 is shown in figure 19. although the component values given in figure 19 are based on a 5 v @ 4 a /3.3 v @ 4 a/2.5 v @ 1.5 a design, the ADP3020 output drivers are capable of handling out- put currents anywhere from <1 a to over 10 a. throughout this section, design examples and component values will be given for three different p ower levels. for simplicity, these levels will be referred to as low power, basic, and extended power. table iii shows the input /output speci?cations for these three levels. table iii. typical power level examples extended low power basic power input voltage range 5.5 v to 25 v 5.5 v to 25 v 5.5 v to 25 v switching output 1 3.3 v/2 a 3.3 v/4 a 3.3 v/10 a switching output 2 5 v/2 a 5 v/4 a 5 v/10 a linear output 2.5 v/1 a 2.5 v/1.5 a 2.5 v/2 a input voltage range the input voltage range of the ADP3020 is 5.5 v to 25 v when 5 v output is desired, and 4.5 v to 25 v when neither switcher output is >4.0 v. this c onverter design is optimized to deliver the best performance within a 7.5 v to 18 v range, which is the nominal voltage for three to four cell li-ion battery stacks. volt- ages above 18 v may occur under light loads and when the system is powered from an ac adapter with no battery installed. maximum output current and mosfet selection the maximum output current for each switching regulator is lim- ited by sensing the voltage drop between the drain and source of the high-side mosfet when it is turned on. a current sense comparator senses voltage drop between cs5 and sw5 for the 5 v converter and between cs3 and sw3 for the 3.3 v converter. the sense comparator threshold is 72 mv when the program- ming pin, clset, is floating, and is 144 mv when clset is connected to ground. current-limiting is based on sensing the peak current. peak current varies with input voltage and depends on the inductor value. the higher the ripple current or input voltage, the lower the converter maximum output current at the set current sense ampli?er threshold. the relation between peak and dc output current is given by: iiv vv flv peak out out in max out in max =+ ? ? ? ? ? ? () () C 2 (2) at a given current comparator threshold v th and mosfet r ds(on) , the maximum inductor peak current is: i v r peak th ds on = () (3) rearranging equation 2 to solve for i out(max) gives: i v r v vv flv out max th ds on out in max out in max () () () () C C = ? ? ? ? ? ? 2 (4) normally, v th should be set to its maximum value of 144 mv. for example, in the circuit of figure 19, an si4410, which has an r ds(on) of 13.5 m ? would have a maximum peak current limit of around 10 a. a less ef?cient way to achieve maximum power from the converter is to design the inductor with a larger inductance, (i .e., a lower ripple current). this helps reduce the peak-to-dc current ratio and increases maximum converter output, but may also increase the inductor value and its size. it is important to remember that this current limit circuit is designed to protect against high current or short circuit condi- tions only. this will protect the ic and mosfets long enough to allow the output undervoltage protection circuitry to latch off the supply.
ADP3020 13 rev. 0 c14a 10 f c14b 10 f d2 10bq040 l2 6.8 h r2 130k 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 cs5 fb5 ean5 eao5 adj/ fx5 ss5 clset5 bst5 drvh5 sw5 drvl5 pgnd sd auxvcc intvcc vin drvl3 sw3 drvh3 bst3 drv2 fb2 sd2 cpor pwrgd pfo ref agnd clset3 mode sync ss3 adj/ fx3 eao3 ean3 fb3 cs3 pfi u1 ADP3020 c1 68pf r10 10k c18 150pf c4 1 f r11 6.2k c19 330pf d6 1n4148 c17 100nf q5 si4410 q4 si4410 c16 1 f r6 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 d4 10bq040 (optional) c27a 68 f c27b 68 f v out5 5v, 4a ++ d3 10bq040 (optional) c24a 68 f c24b 68 f v out33 3.3v, 4a ++ q2 si4410 q5 si4410 100nf c15 4.7 f c13 1 f c20a 10 f c20b 10 f d1 10bq040 l1 6.8 h c26 4.7 f v out25 2.5v, 1.5a r9 47k c28 1 f r17 1k r8 13k r7 12k c11 33 f r24 210k r26 60.4k c12 r12 10k r13 10k pwrgd pfo r14 4.7 c22 4.7 f vin 5.5v-25v r2 47k r3 47k c5 1nf r4 75k c8 470pf c9 68pf c6 1 f d5 1n4148 r5 10 c2 330pf q1 irf7404 figure 19. 45 w, triple output dc-dc converter
ADP3020 14 rev. 0 nominal inductor value the inductor design is based on the assumption that the induc- tor ripple current is 30% of the maximum output dc current at nominal 12 v input voltage. the inductor ripple current and inductance value are not critical, but this choice is quite impor- tant in analyzing the trade-offs between cost, size, ef?ciency, and volume. the higher the ripple current, the lower the induc- tor size and volume. however, this will lead to higher ac losses in the windings. conversely, a higher inductor value means lower ripple current and smaller output ?lter capacitors, but transient response will be slower. the design of the inductor should be based on the maximum output current plus 15% (1/2 of the 30% ripple allowance) at the nominal input voltage: lv v v vif in nom out out in nom out ? () 3 () () C (5) optimum standard inductor values for the three power levels are shown in table iv. table iv. standard inductor values freq. 3.3 v/2 a 3.3 v/4 a 3.3 v/10 a 5 v/2 a 5 v/4 a 5 v/10 a 200 khz 20 h 8.2 h 3.3 h 22 h 10 h 4.7 h 300 khz 12 h 6.8 h 2.2 h 15 h 8.2 h 3.3 h 400 khz 10 h 4.7 h 1.5 h 10 h 6.8 h 2.2 h inductor selection once the value for the inductor is known, there are two ways to proceed; either to design the inductor in-house or to buy the closest inductor that meets the overall design goals. standard inductors buying a stand ard inductor will provide the fastest, easiest solu- tion, and many companies offer suitable power inductor solutions. a list of power inductor manufacturers is given in table v. designing the inductor in-house core material concerns there are several good choices for low core loss materials at high frequency. two examples are distributed gap kool mu powdered cores from magnetics and soft ferrite cores, material 3f3, 3f4, 3d3, or 4c4, from philips. to minimize the ac core loss, especially when the inductor value is relatively low and ripple current is high, the use of low frequency powdered iron cores and low frequency ferrite cores (speci?ed for frequency up to 100 khz) should be avoided. the ripple current is a key fac- tor for op timization of the converter design and determines core losses to a large extent. selecting a high ripple current means a relatively low inductor value. this, for a given core size, reflects a lower number of turns and higher core loss. core geometry there are two main categories of ferromagnetic cores that could be used in this type of application. open magnetic loop types such as beads, beads on leads, rods, and slugs provide the low- est cost, but do not have focused magnetic ?elds in the core. the radiated emi distributed around the magnetic ?eld may create problems with noise interference in electronic circuits surrounding the choke. other types are cores with closed mag- netic paths, such as pot cores, pq, u, and e cores, toroids, etc. the cost of these cores is higher, but emi and rfi performance is better. a good compromise between price and performance are cores with a toroidal shape, used primarily in through-hole printing board designs. a very cost-effective solution based, not on closed-loop core, but on good shielded open-loop core, are surface-mount power inductors, do, dt, and ds series from coilcraft. table v. recommended inductor manufacturers murata electronics coilcraft coiltronics north america inc. phone: 847/639-6400 phone: 561/241-7876 phone: 770/436-1300 fax: 847/639-1469 fax: 561/241-9339 fax: 770/436-3030 web: www.coilcraft.com web: www.coiltronics.com web: www.murata.com smt power inductors, smt power inductors, smt power inductors, series 1608, 3308, 3316, 5022, 5022hc, series uni-pac2, uni-pac3 and uni-pac4, series lqt2535 do3340, low cost solution low cost solution best for low emi/rfi smt shielded power inductors, smt power inductors, series ds5022, ds3316, dt3316, series, econo-pac, versa-pac, best for low emi/rfi best for low pro?le or flexible design. power inductors and chokes, power inductors ctx series, chip inductors series dc1012, pcv-0, pcv-1, pcv-2, low emi/rfi, low cost toroidal inductors lqn6c, lqs66c pch-27, pch-45, low cost but not miniature.
ADP3020 15 rev. 0 the design the details of designing the power inductor are covered in many reference texts, and will not be covered here. examples of soft- ware and reference books that can be used for quick design of the power inductor are given below: softwaremagnetic designer from intusoft, www.intusoft.com designing magnetic components for high frequency dc-dc converters, mclyman, kg magnetics inc., isbn 1-883107-00-08 (for advanced users) power supply cookbook, marty brown, edn series for design engineers, isbn 0-7506-9442-4 (for beginners and intermediate users) c in and c out selection in continuous conduction mode, the source current of the upper mosfet is approximately a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: ivvv i v rms out in out max in ? () C (6) this formula has a maximum at v in = 2 v out , where i rms = i out /2. note that the capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. if electrolytic or tantalum capacitors are used, an addi- tional 0.1 fC1 f ceramic bypass capacitor should be placed in parallel with c in . the selection of c out is driven by the required effective series resistance (esr) and the desired output ripple. a good rule of thumb is to limit the ripple voltage to 1% of the nominal output voltage. it is assumed that the total ripple is caused by two factors: 25% comes from the c out bulk capacitance value, and 75% comes from the capacitor esr. the value of c out can be deter- mined by: c i fv out ripple ripple = 2 (7) where i ripple = 0.3 i out and v ripple = 0.01 v out . the maximum acceptable esr of c out can then be found using: esr v i ripple ripple ? 075 . (8) manufacturers such as vishay, avx, elna, wima and sanyo provide good high-performance capacitors. sanyos oscon semiconductor dielectric capacitors have lower esr for a given size, at a somewhat higher price. choosing suf?cient capacitors to meet the esr requirement for c out will normally exceed the amount of capacitance needed to meet the ripple current requirement. in surface-mount applications, multiple capacitors may have to be paralleled to meet the capacitance, esr, or rms current handling requirements. aluminum electrolytic and dry tantalum capacitors are available in surface-mount con?gurations. in the case of tantalum, it is critical that capacitors are surge tested for use in switching power supplies. recommendations for output capacitors are shown in table vi. power mosfet selection n-channel power mosfets must be selected for use with the ADP3020 for both the main and synchronous switch. the main selection parameters for the power mosfets are the threshold voltage (v gs(th) ) and on-resistance (r ds(on) ). an internal ldo generates a 5 v supply that is boosted above the input voltage using a bootstrap circuit. this floating 5 v supply is used for the upper mosfet gate drive. logic-level threshold mosfets must be used for both the main and synchronous switches. maximum output current (i max ) determines the r ds(on) require- ment for the two power mosfets. when the ADP3020 is operating in continuous mode, the simplifying assumption can be made that one of the two mosfets is always conducting the load current. the duty cycles for the mosfets are given by: upper mosfet duty cycle v v out in = (9) lower mosfet duty cycle vv v in out in = C (10) table vi. recommended capacitor manufacturers maximum output current 2 a 4 a 10 a input capacitors tokin multilayer tokin multilayer tokin multilayer ceramic caps, 22 f/25 v ceramic caps, 2 22 f/25 v ceramic caps, 2 22 f/25 v p/n: c55y5u1e226z p/n: c55y5u1e226z p/n: c55y5u1e226z taiyo yuden inc. taiyo yuden inc. vishey ceramic caps, ceramic caps, y5v series ceramic caps, y5v series z5u series, 2 15 f/25 v 10 f/25 v 2 10 f/25 v p/n: tmk432bj106km p/n: tmk432bj106km output capacitors sanyo poscap tpc sanyo poscap tpc sanyo poscap tpb +3.3 v output series, 68 f/10 v series, 2 68 f/10 v series, 2 220 f/4.0 v output capacitors sanyo poscap tpc sanyo poscap tpc sanyo poscap tpb +5 v output series, 68 f/10 v series, 2 68 f/10 v series, 2 330 f/6.3 v
ADP3020 16 rev. 0 from the duty cycle, the required minimum r ds(on) for each mosfet can be derived by the following equations: upper mosfet: r upper vp vi t ds on in d out max () () = + () 2 1 ? (11) lower mosfet: r lower vp vv i t ds on in d in out max () () C = () + () 2 1 ? (12) where p d is the allowable power dissipation and is the tempera- ture dependency of r ds(on) . p d will be determined by ef?ciency and/or thermal requirements (see ef?ciency ). (1 + ? t ) is gen- erally given for a mosfet in the form of a normalized r ds(on) vs. temperature curve, but = 0.007/ c can be used as an approximation for low voltage mosfets. maximum mosfet power dissipation occurs at maximum output current, and can be calculated as follows: upper mosfet: p upper v v ir t d out in max ds on () ( ) () = + 2 1 ? (13) lower mosfet: p lower vv v ir t d in out in max ds on () C () () =+ 2 1 ? (14) the schottky diode, d1 shown in figure 19, conducts only during the dead time between conduction of the two power mosfets. d1s purpose is to prevent the body-diode of the lower n-channel mosfet from turning on and storing charge during the dead time, which could cost as much as 1% in ef?ciency. d1 should be selected for forward voltage of less than 0.5 v when conducting i max . recommended transistors for upper and lower mosfets are given in table vii. table vii. recommended mosfets maximum output 2 a 4 a 10 a vishay/ si4412dy, si4410dy, si4874dy, siliconix 28 m ? 13.5 m ? 7.5 m ? international irf7805, irf7811, irfba3803, recti?er 11 m ? 8.9 m ? 5.5 m ? irf7805, irf7809, 11 m ? 7.5 m ? soft start the soft-start time of each of switching regulator can be pro- grammed by connecting a soft-start capacitor to the corresponding soft-start pin (ss3 or ss5). the time it takes each regulator to ramp up to its full duty ratio depends proportionally on the values of the soft-start capacitors. the charging current is 4 a 20%. the capacitor value to set a given soft-start time, t ss , is given by: ca t v pf ss ss ?? () 4 26 . () (15) fixed or adjustable output voltage each switching controller of the ADP3020 can be programmed to operate with a ?xed or adjustable output voltage. as shown by the general application schematic in figure 19, putting the ADP3020 into ?xed mode gives a nominal output of 3.3 v and 5 v for the two switching buck converters. by using two identi- cal resistor dividers per converter, any output voltage between 1.25 v and vinC0.5 v can be set. the center point of one divider is connected to the feedback pin, fb, and the center point of the other identical divider is connected to ean. it is important to use 1% resistors. a good value for the lower leg resistors is 10 k ? , 1%, then the upper leg resistors for a given output voltage can be determined by: r vv k upper out =? C. . () 12 012 (16) table viii shows the resistor values for the most common out- put voltages. table viii. typical feedback resistor values v out 1.25 v 1.3 v 1.5 v 1.8 v 2.0 v 2.5 v 3.0 v 3.3 v 5.0 v r upper 412 ? 825 ? 2.49 k ? 4.99 k ? 6.65 k ? 10.7 k ? 15.0 k ? 17.4 k ? 31.6 k ? r lower 10 k ? 10 k ? 10 k ? 10 k ? 10 k ? 10 k ? 10 k ? 10 k ? 10 k ?
ADP3020 17 rev. 0 pwm mode/power-saving (psv) mode operation the mode of operation for both switching regulators can be preset using the mode pin. when mode is high, or connected to intvcc, both converters work only in pwm mode, regardless of output current. mode connected to gnd makes both con- verters operate in a dual pwm/psv mode of operation. in dual mode, each converter has its own boundary output current when the converter switches from psv mode to pwm mode and vice versa. there is an output current hysteresis for each mode tran- sition to avoid improper operation. there are several design recommendations regarding dual mode operation. the trip output current level for switching between pwm mode and psv mode is a percentage of the peak current sensed via the internal current sense comparator. however, the value of that current depends on the r ds(on) of the upper mosfet. for example, if the design uses an si4420 versus an si4410 power mosfet (9 m ? vs. 13.5 m ? ) the maximum output power of the converter and the mode trip output current will both be 50% higher. ef?ciency enhancement the ef?ciency of each switching regulator is inversely propor- tional to the losses during the switching conversion. the main factors to consider when attempting to maximize ef?ciency are: 1. resistive losses, which include the r ds(on) of upper and lower mosfets, trace resistances and output choke wire resistance. these losses contribute a major part of the overall power loss in low voltage battery-powered applications. however, trying to reduce these resistive losses by using multiple mosfets and thick traces may tend to lead to lower ef?ciency and higher price. this is due to the trade-off between reduced resistive loss and increased gate drive loss that must be considered when optimizing ef?ciency. 2. switching losses due to the limited time of switching transitions. this occurs due to gate drive losses of both upper and lower mosfets, and switching node capacitive losses, as well as through hysteresis and eddy-current losses in power choke. input and output capacitor ripple current losses should also be considered as switching losses. these losses are in put- voltage-dependent and can be estimated as follows: pvicf swloss in max sn = 25 185 . . (17) where c sn is the overall capacitance of the switching node related to loss. 3. supply current of the switching controller (independent of the input current redirected to supply the mosfets gates). this is a very small portion of the overall loss, but it does increase with input voltage. transient response considerations both stability and regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in output load current. when a load step occurs, output voltage shifts by an amount equal to the current step multiplied by the total esr of the summed output capacitor array. output overshoot or ringing during the recovery time (in both directions of the current step change) indicates a stability problem. the external feedback compensation compo- nents shown in figure 18 should provide adequate compensation for most applications. feedback loop compensation the ADP3020 uses voltage mode control to stabilize the switch- ing controller outputs. figure 20 shows the voltage mode control loop for one of the buck switching regulators. the internal refer- ence voltage v ref is applied to the positive in put of the internal error ampli?er. the other input of the error ampli?er is ean, and is internally connected to the feedback sensing pin fb via an internal resistor. the error ampli?er creates the closed-loop voltage level for the pulsewidth modulator that drives the external power mosfets. the output lc ?lter smooths the pulse- width modulated input voltage to a dc output voltage. v out c out l1 pwm comparator ADP3020 vin drvh drvl parasitic esr eao ean ref r1 r3 c1 c2 c3 r2 fb v ramp figure 20. buck regulator voltage control loop the pulsewidth modulator transfer function is v out /vea out , where vea out is the output voltage of the error ampli?er. that function is dominated by the impedance of the output ?lter with its double-pole resonance frequency (f lc ) and a single zero at output capacitor (f esr ) and the dc gain of the modulator, equal to the input voltage divided by the peak ramp height (v ramp ), which is equal to v ref (1.2 v): f lc lc f out = 1 2 (18) f esr c esr out = 1 2 (19)
ADP3020 18 rev. 0 the compensation network consists of the internal error ampli- ?er and two external impedance networks z in and z fb . once the application and the output ?lter capacitance and esr are chosen, the speci?c component values of the external impedance net- works z in and z fb can be determined. there are two design criteria for achieving stable switching regulator behavior within the line and load range. one is the maximum bandwidth of the loop, which affects fast transient response, if needed, and the other is the minimum accepted by the design phase margin. the phase margin is the difference between the closed-loop phase and 180 degrees. recommended phase margin is 45 to 60 degrees for most applications. the equations for calculating the compensation poles and zeros are: f r cc cc p 1 1 22 12 12 = + (20) f rc p 2 1 233 = (21) f rc z 1 1 221 = (22) f rr c z 2 1 2133 = + () (23) the value of the internal resistor r 1 is 71 k ? for the 3.3 v switching regulator, and 128 k ? for the 5 v switching regulator. compensation loop design and test method 1. choose the gain (r2/r1) for the desired bandwidth. 2. place f z1 20%C30% below f lc . 3. place f z2 20%C30% above f lc . 4. place f p1 at f esr , check the output capacitor for worst-case esr tolerances. 5. place f p2 at 40%C60% of oscillator frequency. 6. estimate phase margins in full frequency range (zero frequency to zero gain crossing frequency). 7. apply the designed compensation and test the tran sient response under a moderate step load change (30%C60%) and various input voltages. monitor the output voltage via oscilloscope. the voltage overshoot or undershoot should be within 1%C3% of the nominal output, without ringing and abnormal oscillation. additional application circuits the multiple outputs and wide input voltage range of the ADP3020 make it a very flexible ic for use in a wide variety of appli cations. for example, the ADP3020 can be used to generate low voltage (<4.0 v) outputs from a 5 v supply. the circuit shown in fig- ure 21 converts the 5 v input into a 3.3 v and a 2.5 v output. the circuit of figure 22 uses a secondary winding on the 5 v output to generate an unregulated 15 v rail which is then regu- lated to 12 v by the ldo output of the ADP3020.
ADP3020 19 rev. 0 c14a 10 f c14b 10 f d2 10bq040 l2 4.7 h r1 6.9k 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 cs5 fb5 ean5 eao5 adj/ fx5 ss5 clset5 bst5 drvh5 sw5 drvl5 pgnd sd auxvcc intvcc vin drvl3 sw3 drvh3 bst3 drv2 fb2 sd2 cpor pwrgd pfo ref agnd clset3 mode sync ss3 adj/ fx3 eao3 ean3 fb3 cs3 pfi u1 ADP3020 c1 150pf r16 10k c4 1 f r11 6.2k c19 330pf d6 1n4148 c17 100nf q5 si4410 q4 si4410 c16 1 f r6 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 d4 10bq040 (optional) c27a 68 f c27b 68 f v out25 2.5v, 3a ++ d3 10bq040 (optional) c24a 68 f c24b 68 f v out33 3.3v, 4a ++ q2 si4410 q5 si4410 c15 4.7 f c13 1 f c20a 10 f c20b 10 f d1 10bq040 l1 4.7 h c26 4.7 f v out15 1.5v, 1.5a r9 4.7k c28 1 f r17 100 r8 3.16k r7 12k c11 33 f c12 100nf r12 10k pwrgd r14 4.7 c22 4.7 f v in 4.5v-5.5v r2 47k r3 47k c5 1nf r4 75k c8 470pf c9 68pf c6 1 f r15 10.7k d5 1n4148 r5 10 r10 2.2k c18 2.2nf r13 4.7 c2 6.8nf q1 nds8434 figure 21. 5 v to 2.5 v/3.3 v dc-dc converter
ADP3020 20 rev. 0 layout considerations the following guidelines are recommended for optimal perfor- mance of a switching regulator in a portable pc system: general recommendations 1. for best results, a four-layer (minimum) pcb is recom- mended. this should allow the needed versatility for control circuitry interconnections with optimal placement, a signal ground plane, power planes for both power ground and the input power, and wide interconnection traces in the rest of the power delivery current paths. each square unit of 1 ounce copper trace has a resistance of ~ 0.53 m ? at room temperature. 2. whenever high currents must be routed between pcb layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 3. the power and ground planes should overlap each other as little as possible. it is generally easiest (although not neces- sary) to have the power and signal ground planes on the same pcb layer. the planes should be connected nearest to the ?rst input capacitor where the input ground current flows from the converter back to the battery. c14a 10 f c14b 10 f d2 10bq040 l2* r1 130k 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 cs5 fb5 ean5 eao5 adj/ fx5 ss5 clset5 bst5 drvh5 sw5 drvl5 pgnd sd auxvcc intvcc vin drvl3 sw3 drvh3 bst3 drv2 fb2 sd2 cpor pwrgd pfo ref agnd clset3 mode sync ss3 adj/ fx3 eao3 ean3 fb3 cs3 pfi u1 ADP3020 c1 68pf r10 10k c18 150pf c4 1 f r11 6.2k c19 330pf d6 1n4148 c17 100nf q5 si4410 q4 si4410 c16 1 f r6 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 c27a 68 f c27b 68 f v out5 5v, 4a ++ c24a 68 f c24b 68 f v out33 3.3v, 4a ++ q2 si4410 q3 si4410 c15 4.7 f c13 1 f c14a 10 f c14b 10 f d1 10bq040 l1 6.8 h c31 4.7 f v out12 12v, 100ma r9 4.7k c28 1 f r17 1k r8 9.09k r7 1k c32 4.7 f r24 210k r26 60.4k c12 100nf r12 10k r13 10k pwrgd pfo r14 4.7 c22 4.7 f vin 5.5v-25v r2 47k r3 47k c5 1nf r4 75k c8 470pf c9 68pf c6 1 f d5 1n4148 r5 10 n2 n1 *l2 4.7 h n2/n1 =2:1 c2 330pf q1 2n3906 d11 1n4148 figure 22. using a secondary winding and an ldo post regulator to generate 12 v
ADP3020 21 rev. 0 4. if critical signal lines (including the voltage and current sense lines of the ADP3020) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the sig- nals at the expense of making signal ground a bit noisier. 5. the pgnd pin of the ADP3020 should connect ?rst to a ceramic bypass capacitor on the vin pin, and then into the power ground plane using the shortest possible trace. how- ever, the power ground plane should not extend under other signal components, including the ADP3020 itself. if neces- sary, follow the preceding guideline to use the signal plane as a shield between the power ground plane and the signal circuitry. 6. the agnd pin of the ADP3020 should connect ?rst to the ref capacitor, and then into the signal ground plane. in cases where no signal ground plane can be used, short interconnec- tions to other signal ground circuitry in the power converter should be used. 7. the output capacitors of the power converter should be connected to the signal ground plane even though power current flows in the ground of these capacitors. for this reason, it is advised to avoid critical ground connections (e.g., the signal circuitry of the power converter) in the signal ground plane between the input and output capacitors. it is also advised to keep the planar interconnection path short (i.e., have input and output capacitors close together). 8. the output capacitors should also be connected as closely as possible to the load (or connector) that receives the power. if the load is distributed, the capacitors should also be dis- tributed, and generally in proportion to where the load tends to be more dynamic. 9. absolutely avoid crossing any signal lines over the switching power path loop, described below. power circuitry 10. the switching power path should be routed on the pcb to encompass the smallest possible area in order to minimize radiated switching noise energy (i.e., emi). failure to take proper precaution often results in emi problems for the entire pc system as well as noise-related operational prob- lems in the power converter control circuitry. the switching power path is the loop formed by the current path through the input capacitors, the two fets (and the power schottky diode if used), including all interconnecting pcb traces and planes. the use of short and wide interconnection traces is especially critical in this path for two reasons: it mini- mizes the in ductance in the switching loop, which can cause high-energy ringing, and it accommodates the high current demand with minimal voltage loss. 11. a power schottky diode (1 ~ 2 a dc rating) placed from the lower fets source (anode) to drain (cathode) will help to minimize switching power dissipation in the upper fet. in the absence of an effective schottky diode, this dissipation occurs through the following sequence of switching events. the lower fet turns off in advance of the upper fet turning on (necessary to prevent cross-conduction). the circulating current in the power converter, no longer ?nding a path for current through the channel of the lower fet, draws cur- rent through the inherent body-drain diode of the fet. the upper fet turns on, and the reverse recovery char- acteristic of the lower fets body-drain diode prevents the drain voltage from being pulled high quickly. the upper fet then conducts very large current while it momentarily has a high voltage forced across it, which trans- lates into added power dissipation in the upper fet. the schottky diode minimizes this problem by carrying a majority of the circulating current when the lower fet is turned off, and by virtue of its essentially nonexistent reverse recov- ery time. 12. whenever a power-dissipating component (e.g., a power mosfet) is soldered to a pcb, the liberal use of vias, both directly on the mounting pad and immediately sur- rounding it, is recommended. two important reasons for this are: improved current rating through the vias (if it is a current path), and improved thermal performance, espe- cially if the v ias are extended to the opposite side of the pcb where a plane can more readily transfer the heat to the air. 13. the output power path, though not as critical as the switch- ing power path, should also be routed to encompass a small area. the output power path is formed by the current path through the inductor, the output capacitors, and back to the input capacitors. 14. for best emi containment, the power ground plane should extend fully under all the power components except the output capacitors. these are: the input capacitors, the power mosfets and schottky diode, the inductor, and any snub- bing elements that might be added to dampen ringing. avoid extending the power ground under any other circuitry or signal lines, including the voltage and current sense lines. signal circuitry 15. the cs and sw traces should be kelvin-connected to the upper mosfet drain and source so that the additional voltage drop due to current flow on the pcb at the current sense comparator connections does not affect the sensed voltage. it is desirable to have the ADP3020 close to the out- put capacitor bank and not in the output power path, so that any voltage drop between the output capacitors and the agnd pin is minimized, and voltage regulation is not compromised.
ADP3020 22 rev. 0 outline dimensions dimensions shown in inches and (mm). 38-lead tssop (ru-38) 38 20 19 1 0.386 (9.80) 0.378 (9.60) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0200 (0.50) bsc 0.0433 (1.10) max 0.0106 (0.27) 0.0067 (0.17) 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 0.252 (6.40) bsc c3773 5 4/00 (rev. 0) printed in u.s.a.

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